Architectural Level Sub-threshold Leakage Power Estimation of SRAM Arrays with its Peripherals

In this work, an analytical model for estimation of width scalable architectural level leakage current of the 6T Static Random Access Memory (SRAM), considering its peripherals is proposed in 45nm technology. Based on the mode of operation of SRAM (read, write and idle phase), the width dependent leakage current is estimated at an early stage which reduces design time and aid to power management. Finally, a SRAM structure (i.e. rows and columns) dependent model has been evaluated. Referring circuit simulator (HSPICE) as golden result, the proposed model shows a high accuracy with error margin less than 5%. The results are 143,127 and 330 times faster than that achieved by HSPICE simulation in idle, read and write phase respectively.